Welcome to Robot Dialogs. This is a place where I will record my progress, mistakes, errors, failures, lessons learned and hopefully occasional success in my designs and implementations of robots and other technical endeavors. I will try to make it as educational, informative and entertaining as I can...

Sunday, July 10, 2022

Eurorack Noise Generator v1

When I bought the AS3310 chips from Electric Druid for the polyphonic envelope I also bought a few other chips to experiment with. One that I expected to be a pretty straight forward project to set up for a module was the Noise2.  

The chip is just an 8 pin PIC preprogrammed to output white and pink noise. There's a thorough writeup on the development of the firmware here.

Only 4 pins on the Noise2 are used and it's all 0 to 5V so interfacing is pretty easy. I wanted both filtered and unfiltered white noise and a pink noise output all buffered to prevent undo current draw on the Noise2 chip and amplified to 0 to 10V in my setup which required 3 op-amps. That left one op-amp available so I also have an inverted filtered white noise. With 4 outputs the jacks on the module could be on top and bottom and support the PCB properly.

The filter in this case is a simple RC low pass filter straight off the data sheet.

I went about simulating the circuit and then breadboarding it to confirm my schematics.

Simulation of the filter and output buffer with inversion: see it live


The PCB design went fast relative to some other designs. Having 3d models for parts and a template worked out for starting designs has helped speed up the work. I used TL072s instead of a TL074 (as shown in the breadboard) mainly because I have more of them available.

Assembly is pretty quick with so few components:
  1.  Surface Mount Resistors
  2.  Ceramic caps first, the solder points are below sockets on the top side.
  3.  IC Sockets
  4.  Diodes and Ferrite Beads
  5.  Polarized Caps
  6.  2x5 Power Socket
  7.  7805 Regulator
  8.  Jacks, aligned to panel
Testing went well, there haven't really been too many surprises on this design. The only potential problem I thought I had was a -6V spike on the unfiltered white noise output's falling edges, but I haven't observed that when the output is connected, only when it's floating, so I'm not going to stress about it.

Here are a few scope images showing the outputs:
Unfiltered White Noise and Filtered White Noise
Unfiltered White Noise and Pink Noise
Filtered White Noise and Inverted Filtered White Noise (with math adding them together there in the middle).

Power consumption of the module is 21mA on the +12V rail and 7mA on the -12V rail.

Once again I had a friend with a mill help me with some front panels with engraving. The width is 4HP (20.32 mm).


The depth is ~32mm but can be improved with a lower profile 5V regulator... something to change in v2.

Other thoughts for a v2:

  •  Use better footprint for polarized caps.
  •  Add alternate 7805 footprint for T0-92 or surface mount.

Eurorack Level Display v2

 A quick update now that I've received version 2 of the Level PCB. (For more info see v1 details here.)

The PCB with LEDs is virtually identical to the v1 version. The only real difference was that I panelized the design to get more of them for v2. 


On the PCB that handles signals and power, a lot of changes were made.

  1. Used different footprint for resistors.
  2. Used wider footprints for caps I have that are 5mm pitch.
  3. Avoided collisions between the arduino header footprint and other components.
  4. Moved the 20pin header to allow for less depth overall.
  5. Used more consistent trace sizes.
  6. Added a path between the two potential inputs that can be jumpered so that the two inputs are multipled together. In using the module I find two inputs unhelpful typically. When the jumper is bridged, R20, R21, R22 and C2 aren't required.
  7. Removed a log of capacitors.
  8. Removed the 5V regulator, and rely on the arduino pro mini's regulator.
  9. Removed power LED.
  10. Removed mounting holes.
All of that allowed for a PCB small enough to panelize and reduced the overall depth considerably.




If I ever make a v3 I think a CV input might be useful. It could be picked up on the analog inputs of the Arduino and displayed on the LEDs similar to how the tuner modification in the v1 post works.

On the software side I haven't changed much. When I use the jumper on v2 to multiple the two inputs together I disable the other input (A7 usually) so that the update rate is better and there aren't and noise issues from a floating pin. 

With the help of a friend the front panels are also evolving. We're figuring out engraving the labeling and also combining multiple of the modules on the same panel.

Eurorack Polyphonic Envelope Generator v1

This post is about a DIY design of a polyphonic envelope eurorack module.

The idea for this module started after I bought a second hand Roland System-8 and started to understand the polyphonic features better. I had already built several oscilators from a few DIY kit providers and was running into the issue of not having enough envelopes for them all. So decided to try and build a polyphonic envelope.

I jumped right into this design with a chip selection, I went over to Electric Druid and grabbed a few AS3310 ADSR chips to experiment with. I didn't have any modules that used this chip but while breadboarding a design I came across a useful reference on Eddy Bergman's site. Ultimately my goals of a polyphonic version complicated the design a bit.

One thing to note on the AS3310 is that is has some odd control voltages, particularly the Attack, Decay and Release CVs are 0 to -5V instead of 0 to +5V like the Sustain CV. I wanted 0 to 10V tolerant CV inputs and potentiometers too. To solve that oddity I decided to simulate the CV input buffering I'd need to work with the chips.

Sustain CV Simulation: see it live

Attack, Decay, Release CV simulation: see it live

For the Gate inputs I also wanted 10V tolerance, so I used an op-amp there to buffer and amplify it before the chip sees it.

Gate simulation: see it live

On the output side I wanted to amplify the AS3310's 0 to 5V outputs to 0 to 10V and also wanted to have a buffer between the output jack and the chip. 

Output Buffer Simulation: see it live

With some simulations functional I went about breadboarding the design to see if it would work as expected. For the breadboard version I only used one AS3310, so it's not polyphonic yet, I just wanted to prove the ideas and circuits before adding more complexity.

That worked out pretty well. I can safely say it's the most complicated thing I've put on a breadboard since college.

After that I designed a version with 4 AS3310's to make the first version of the polyphonic envelope module in KiCAD. One thing I discovered during this was that the hierarchical sheets are a useful way to organize parts when they're added to the PCB. If every part of the schematic was on one page, then all the parts for the design get jumbled together on the PCB, but the parts in a hierarchical sheet are separate from the rest. So in the schematic files there are several sheets to take advantage of this quirk and also it makes block diagrams of the overall design as a side effect.

On the PCB I also added a switch to bypass the gate and trigger all the envelopes for testing. Unfortunately I didn't simulate that idea, or breadboard it, so it was wrong. On the versions I've built so far I just leave a few components out and only the first envelope uses the switch. More on that later.

The PCB was complicated. I was set on a two layer PCB and very quickly I switched the resistors on the BOM to be surface mount instead of through hole. I think I routed the PCB two or three times from scratch before I ordered them.

I ordered the v1 PCBs for this on January 13th. I didn't receive them until late in April. I used the service Seeed Fusion which has very inexpensive boards, but I learned from this order that you should always choose the fast shipping option(s). They simply sat on this design for almost 4 months before it moved through production. I reached out to them several times and got excuses for holidays and lockdowns, but I also ordered other designs after these and received them before these, so I have a hard time trusting those excuses.

Assembly order is unique to every PCB depending on the BOM, here's the order I assembled in:
  1.  Resistors - all surface mount components, both sides of the PCB.
  2.  Diodes and Ferrites
  3.  Small Caps
  4.  Sockets
  5.  Large Caps
  6.  Transistors
  7.  Trim Pots
  8.  Jacks, LED and Pots in panel

Problems on v1 PCB:
  • Output LEDs always were always on.
    • Reversed transistors. See orientation in sim
    • Fix: rotate Q1,Q2,Q3,Q4 180 (swap collector/emitter in schematic)
  • Only first envelope working. - didn't solder U7 properly...
  • Switch triggers first envelope. 
So far I've built two of the envelopes and tested/used them in my synth. 

2022-08-16 Testing:
On the third v1 build of this I discovered that the attack and decay times weren't respected when a gate signal was used. On the scope it looked a lot like the 'Q1 Disabled ***' note in the datasheet. So I started to probe around for that issue. I also checked the gate button, but it seems to work most of the time. 

Eventually I discovered the trigger pin on the chip wasn't really changing when an LFO or similar signal was passed in. It seems those signals didn't have sharp enough edges to cause the trigger spike needed.

I played around with the simulation a bit an found that a larger value decoupling cap on the trigger improves the trigger signal timing. On hardware a 1uF (instead of 3nF) seems to work. It's probably too big but it's available and functions. Some simulation.

Here's a scope image showing the trigger (channel 2) missing on the rising edge of the gate (channel 1).
After swapping for the 1uF trigger cap it's better:

Changes for v2:
  • Fix transistor orientation.
  • Move R15 label it's confusing.
  • Make all U# labels visible, not hidden by chips/sockets.
  • Remove R4, R6 and R16 or fix gate switch circuit.
    • Need to figure out a way for switch to trigger but not allow other gates to go high. Maybe tie it to trig input on AS3310 and remove ugly 3nF?
  • Label Pots on silkscreen
  • Some CV pots might not be needed? Investigate.
  • 3nF caps might not be needed. Need to evaluate v1 PCB with other values.
  • Use geographic re-annotate to make the resistor values easier to find during assembly.
Design files and CAD: